My notes:
RISC-V: Reduced instruction set computer, 5th generation. Developed by a community using open source development methods. The ISA is an open specification released under creative commons.
Instruction Set Architecture (ISA) is an abstract model of a computer.
RISC strives for simplicity and efficiency. Lots of registers and a very modest instruction set. Memory access with a few load and store instructions.
RISC-V base integer ISA has 40 instructions.
It has no patents as the RISC-V ISA does not represent any new technology. It’s based on ideas from the 80s.
Designed as a modular ISA, as opposed to incremental like arm cortex.
A RISC-V implementation has a mandatory base ISA and a number of extensions. A common one is RV32IMAC:
RV32I: 32 bit CPU with base integer ISA.
M: multiplication and division extension.
A: atomic instruction extension.
C: compressed instruction extension.
3 privilege levels:
- User mode (u-mode), for use processes.
- Supervisor mode (s-mode) for kernel and device drivers.
- Machine mode (m-mode) for bootloader and firmware.
Variations like hipervisor mode (h-mode).
Higher privilege levels can access control and status registers of less privileged levels.
Unprivileged specification includes the base integer (I), extensions like float (F), double (D), compressed (C) and many more.
Base variants:
- RV32I: integer 32 bit
- RV32E: fewer registers for embedded
- RV64I: integer 64 bit
- RV128I: integer 128 bit
RV32I has 40 instructions for addition, subtraction, bitwise logic, load and store, jumps, branches. 32 CPU registers, 32-bits wide, and program counter. A special register x0, always reads 0.
The application binary interface specifies a purpose for each registry:
x0 → 0
x1 → return address
x2 → stack pointer
x3 → global pointer
x4 → thread pointer
x5 → temporary/alternate link register
x6-7 → temporaries
x8 → saved register/frame pointer
x9 → saved register
x10-11 → function arguments/return address
x12-17 → function arguments
x18-27 → saved registers
x28-31 → temporaries
Control and status registers: 4096 separate 12-bit address space. CPU information like timers, counters, flags, manufacturer information. Designed to control and monitor the processor’s operation. Software adjusts settings, manage exceptions, check status.
ZICSR extension contains instructions for CSR manipulation.
- mstatus: machine status register. Operating mode and privilege level. Interrupt management.
- mepc: machine exception program counter. PC value of the instruction that caused the exception or interruption.
- mtvec: machine trap-vector base address. trap-handler for machine mode, where the processor should jump when an exception occurs.
- mcause: machine cause register. Reason for the most recent exception or interrupt. Distinguishes between exceptions and interrupts.
- misa: machine ISA register. Supported instruction set extensions. Bit width.
Multiplication extension: 8 instructions for multiplication and division. RV64M adds 5 more instructions. For many embedded processors, multiplication can be done in software.
Float extension: single precision floating point arithmetic. 32 bits representation. Registers f0-f31. Operations and conversions between integer and float. Handling not-a-number and infinites. Comparing and rounding.
Double extension: 64 bits representation. f0-f31 are 64 bit wide.
Compressed instructions: 16 bit encoding for a subset of 34 instructions. 50% to 60% of instructions in a program can be replaced with RCV, resulting in 25% to 30% code-size reduction. Some registers are more popular, one operand is usually overwritten, there are preferred immediate values.
A: atomic memory
Q: quad precision, floating point 128 bit-wide.
B: bit manipulation
S: supervisor
H: hypervisor
L: decimal float
P: packed-SIMD
V: vector
ZICSR: CSR registers
Zifencei: instruction memory synchronization
Compilers are informed of the extensions in the target CPU. If the code has a missing instruction, decoding triggers an exception. The CPU software will handle it, possibly emulating the instruction.
RV32I ISA
1 32-bit program counter, 32 32-bit registers x0-x31, 40 32-bit unprivileged instructions in formats R, I, S, B, U. A major opcode in the 7 least significant bits, source registers rs1 in bits 15-19, rs2 in bits 20-24, destination register rd in bits 7-11, function fields func7 in the last 7 bits of R type, func3 in the bits 12-14, immediate fields towards the end (left side) of the instruction, depending on the type.
24 32-bit privileged instructions in format R and I.
Fixed instruction length.
- R-type: Register. two source registers and one destination. Arithmetic logic operations.
- I-type: Immediate. Immediate value, a constant, and a source register. Load operations and arithmetic with immediate value.
- S-type: Store. Subset of I for storing data in memory. A source register, an immediate offset, and a base address.
- B-type: Branch. Conditional, compare two registers.
- U-type: Upper-immediate. Setting the upper bits of a register to a constant. For initializing.
- J-type: Jump. Unconditional jump.
All immediates decode to 32 bits. Encoding varies by instruction.
Missing instructions are implemented as pseudoinstructions. Stack management and call conventions are defined by the ABI.
RISC-V privileged specification was designed to support virtualized systems. Each operating system communicates via a supervisor binary interface with the hypervisor, which provides the supervisor execution environment. The hypervisor communicates using a hypervisor binary interface, with the hypervisor execution environment.
Machine mode
Used for low level access to a hardware platform also used to implement features too difficult or expensive to implement in hardware.
Non-maskable interrupts NMI, for hardware error conditions. They cause an immediate jump to NMI handler running in M-mode. Has an m-cause register.
Physical Memory Attributes PMA, address ranges like memory regions, memory-mapped control registers, empty holes in the address space.
PMA are properties and capabilities of each region:
- supports read, writes, execution
- subword or subblock access
- atomic operations
- cache coherence
Some are fixed at chip design, some at board design, some are configurable at runtime.
Physical memory protection PMP, foundation for a trusted execution environment. PMP limits the physical address accessible by software running on a hardware thread. An optional PMP unit provides per hardware thread machine mode control registers to allow physical memory access privileges (read, write, execute) to be specified for each physical memory region.
Supervisor level mode
Supports page-based virtual memory of 32, 39 and 48 bits.
SFENCE.VMA instruction is used for synchornizing updates between hardware threads.
s-mode is restricted in interactions with hardware. S-level facilities are implementation specific. Sometimes there is an SBI and an SEE, sometimes they are provided directly.
Assembly language
- Instructions: mnemonic + operands
- Registers
- Labels: symbolic names for memory locations, target for jumps.
- Directives: to control the behavior of the assembler.
- Macros: user-defined sequence of instructions
- Pseudoinstructions: translated by the assembler into one or more real instructions.
Directives: non-CPU instructions. Provide information to the assembler, not executed as machine instructions. Control the assembly process, specify data locations, provide information for linkers.
- .align: aligns the location counter to a power of 2 boundary.
- .section: section of the output file where the following data should be placed.
- .byte: defines an array of 8-bit values.
- .half: 16-bit values array.
- .word: 32-bit values array
- .data: start of the data section, to store initialized data.
- .text: start of the code section, where instructions are stored.
- .globl: declare a global symbol, accessible from other files.
- .equ: assigns a value to a symbol, useful for constants.
- .string: defines a string of ASCII characters with a null terminator.
Operands: instruction, destination, source1, source2.