My notes:
RISC-V is a specification of an instruction set architecture (ISA) for 32-bit, 64-bit, and 128-bit microprocessors. RISC-V is an open ISA that allows everyone to build processors conforming to RISC-V without license fees.
Volume I: User-Level ISA contains general information about RISC-V, base instruction sets for 32, 64, and 128 integer architectures, standard extensions of the base instruction sets, and conventions.
Volume II: Privileged Architecture covers information required for programming operating systems or bare metal embedded systems.
Assembly language is the human-readable and writable representation of machine code. It is a hardware-/processor-dependent language.
In general, a processor has a control unit, an arithmetic logic unit, registers, and signal/data lines (bus) for input and output, e.g., to access volatile memory. The control unit has the task of encoding instruction and controlling the program flow. The computer program is located in memory. A special register, the program counter, holds the current instruction location to carry out. An address is used for accessing a concrete storage unit - usually in the size of bytes or multiple of bytes.
A typical RISC processor performs the classic five-stage RISC pipeline:
- instruction fetch (IF)
- instruction decode (ID)
- instruction execute (EX)
- memory access (MEM)
- write back (WB)
Using pipelining, parallel execution of the stages can be achieved.
An assembler or cross assembler for the target architecture translates the source code in an object file. The linker takes the object file and a linker script that specifies how the segments given in the object file should be put together in memory for execution. The result is an executable file.
Ripes is a simulator for illustrating machine code execution on RV32IMC and RV64IMC architectures.
Qemu is a machine emulator which allows you to emulate a full-system or a single program.
Install qemu in Debian:
$ sudo apt install qemu-system-misc qemu-user-static binfmt-support opensbi u-boot-qemu
Install the crosscompiler toolchain:
sudo apt install gcc-riscv64-linux-gnu
Go to Debian Quick Image Baker pre-baked images and download the image for riscv64-virt.
Rename the downloaded file to riscv.qcow2.
Emulate:
$ qemu-system-riscv64 -machine virt -cpu rv64 -m 1G -device virtio-blk-device,drive=hd -drive file=riscv.qcow2,if=none,id=hd -device virtio-net-device,netdev=net -netdev user,id=net,hostfwd=tcp::2222-:22 -bios /usr/lib/riscv64-linux-gnu/opensbi/generic/fw_jump.elf -kernel /usr/lib/u-boot/qemu-riscv64_smode/uboot.elf -object rng-random,filename=/dev/urandom,id=rng -device virtio-rng-device,rng=rng -nographic -append "root=LABEL=rootfs console=ttyS0"
This command is failing. I’m using Ubuntu instead: RISC-V cheat sheet
Install the debugger:
$ sudo apt install gdb-multiarch
Test creating the assembler file example.s with this contents:
.text
.globl _start
_start:
addi x10, x0, 7
addi x17, x0, 93
ecall
Assemble:
$ riscv64-linux-gnu-as -o example.o example.s
Link:
$ riscv64-linux-gnu-ld -o example example.o
Execute:
qemu-riscv64-static example
Check. In bash:
$ echo $?
In fish:
$ echo $status
You should get the 7 as the result.
Disassemble the binary:
$ riscv64-linux-gnu-objdump --full-contents --disassemble example
Debug:
$ qemu-riscv64-static -g 1234 example &
$ gdb-multiarch example
(gdb) target remote :1234:
(gdb) display /3i $pc
The command display /3i $pc shows the next three instructions, the command si (for step instruction) steps one instruction and continue continues the program being debugged. Type q to quit the debugger.
The RISC-V unprivileged ISA describes:
- RV32I (32-bit integer)
- RV32E (32-bit embedded)
- RV64I (64-bit integer)
- RV128I (128-bit integer)
The following extensions are common:
- M: integer multiplication and division
- A: atomic instructions
- F: single-precision floating point
- D: double-precision floating point
- Q: quad-precision floating point
- C: compressed instructions
- V: vector operations
The base ISAs specify 32 registers and the program counter. The registers are named x0 to x31. Extensions can have further registers. The application binary interface (ABI) contains a convention on how the registers should be used when a compiler translates a program in a higher-level language into machine language.
| Register | ABI Name | Description |
|---|---|---|
| x0 | zero | Zero constant |
| x1 | ra | Return address |
| x2 | sp | Stack pointer |
| x3 | gp | Global pointer |
| x4 | tp | Thread pointer |
| x5-x7 | t0-t2 | Temporaries |
| x8 | s0 / fp | Saved / Frame pointer |
| x9 | s1 | Saved register |
| x10-x11 | a0-a1 | Function args. / return values |
| x12-x17 | a2-a7 | Function arguments |
| x18-x27 | s2-s11 | Saved registers |
| x28-x31 | t3-t6 | Temporaries |
| pc | - | Program counter |
To modify data from memory, you have to load it to a register, perform operations with the data, and store it back to memory.
Encoding:
Instructions which use immediate values:
| instruction | name | format | opcode | funct3 | description |
|---|---|---|---|---|---|
addi |
ADD Immediate | I | 0010011 | 0ⅹ0 | rd = rs1 + imm |
xori |
XORImmediate | I | 0010011 | 0ⅹ4 | rd = rs1 ^ imm |
ori |
OR Immediate | I | 0010011 | 0ⅹ6 | rd = rs1 imm |
andi |
AND Immediate | I | 0010011 | 0ⅹ7 | rd = rs1 & imm |
slli |
Shift Left Logical Imm. | I | 0010011 | 0ⅹ1 | imm[11:5]=0x00, rd = rs1 << imm[4:0] |
srli |
Shift Right Logical Imm. | I | 0010011 | 0ⅹ5 | imm[11:5]=0x00, rd = rs1 << imm[4:0] |
srai |
Shift Right Arith. Imm. | I | 0010011 | 0ⅹ5 | imm[11:5]=0x20, rd = rs1 >> imm[4:0] |
slti |
Set Less Than Imm. | I | 0010011 | 0ⅹ2 | rd = (rs1 < imm)? 0:1 |
sltiu |
Set Less Than Imm. Un. | I | 0010011 | 0ⅹ3 | rd = (rs1 < imm)? 0:1 |
Arithmetic and logical operations that use two registers as source and one register as destination:
| instruction | name | format | opcode | funct3 | funct7 | description |
|---|---|---|---|---|---|---|
add |
ADD | R | 0110011 | 0ⅹ0 | 0ⅹ00 | rd = rs1 + rs2 |
sub |
SUB | R | 0110011 | 0ⅹ0 | 0ⅹ20 | rd = rs1 - rs2 |
xor |
XOR | R | 0110011 | 0ⅹ4 | 0ⅹ00 | rd = rs1 ^ rs2 |
or |
OR | R | 0110011 | 0ⅹ6 | 0ⅹ00 | rd = rs1 rs2 |
and |
AND | R | 0110011 | 0ⅹ7 | 0ⅹ00 | rd = rs1 & rs2 |
sll |
Shift Left Logical | R | 0110011 | 0ⅹ1 | 0ⅹ00 | rd = rs1 << rs2 |
srl |
Shift Right Logical | R | 0110011 | 0ⅹ5 | 0ⅹ00 | rd = rs1 >> rs2 |
sra |
Set Right Arith. | R | 0110011 | 0ⅹ5 | 0ⅹ20 | rd = rs1 >> rs2 |
slt |
Set Less Than | R | 0110011 | 0ⅹ2 | 0ⅹ00 | rd = (rs1 < rs2)? 0:1 |
sltu |
Set Less Than Un. | R | 0110011 | 0ⅹ3 | 0ⅹ00 | rd = (rs1 < rs2)? 0:1 |