Computer Architecture with an Industrial RISC-V Core

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RVfpga System

SweRV EH1 Core

  • open surce.
  • by Western Digital.
  • 2-way superscalar. It can execute multiple instructions per clock cycle, in parallel, by using multiple execution units.
  • 9-stage pipeline.
  • in-order.
  • RV32IMC.
  • Separate instruction and data memories (ICCM and DCCM) tightly coupled to the core.
  • 4-way set-associative I$ (instruction cache) with parity or ECC protection.
  • Programmable interrupt controller.
  • Core debug unit compliant with RISC-V debug specification.
  • system bus: AXI4 or AHB-Lite.

SweRVolf SoC

  • From Chips Alliance.
  • Boot ROM, UART, System Controller, and an SPI controller (SPI1)
  • Renamed to VeeRwolf.

SweRVolfX

  • Extended with peripherals: another SPI controller (SPI2), a GPIO, 8-digit 7-segment displays and a PTC.
  • SweRV EH1 uses an AXI bus. Peripherals use a Wishbone bus. So the SoC has an AXI to Wishbone bridge.

RVfpga Nexys

  • SweRVolfX targeted to Nexys A7 FPGA board
  • on-board memory, lite DRAM controller
  • clock generator
  • clock domain
  • bscan logic for the JTAG port.
  • Peripherals: DDR2 memory, UART via USB, SPI memory flash, 16 leds and switches, SPI accelerometer, 8 digit 7-segment displays.

RVfpga Sim

  • targeted for simulation.
  • wrapped in a testbench to be used by Verilator, an HDL simulator.